Our research centres around the implementation of a new CAD tool set for generating asynchronous
circuits from high-level language level-sensitive specifications.
Compared to synchronous CAD tools which are very mature and accepted
by industry, there is still a shortage of mature CAD tools to support
asynchronous circuit designs. We present supporting tools here which
are targetted towards bridging this gap.
One of the reasons for the lack of commercial tools is the level of complexity of
generating complex asynchronous circuits. Global asynchronous control solutions are
error prone and suffer from state explosion problems. Direct mapping approaches attempt overcome this
by using handshake specifications which describe the control and
datapath together. Here we adopt a global direct mapping approach for input commercial language specifications
which covers direct asynchronous mapping at all levels
of the synthesis flow.
Our aim is to avoid the state explosion problem inherent in other asynchronous
tools such as Petrify by using a synthesis
approach which combines the advantages of using a direct mapping method
and using a commercial language such as Verilog (VHDL) as a specification language.
We explore the design
space more like "CAMAD" using high level synthesis, but making
use of a direct mapping approach from an intermediate Petri
net format to generate asynchronous speed independent implementations.
Fig. 1. gives the block diagram which shows the synthesis flow exhibited
by our technique using Verilog as an input behavioural specification language.
Fig. 1. Block diagram of synthesis flow.
In our toolflow high-level commercial language descriptions e.g. Verilog (VHDL) are
initially compiled and converted into a novel intermediate Petri-net format.
The intermediate format is subsequently used as a medium for Direct mapping to asynchronous circuits.
The control nets are split into two types for
mapping: (i) global control nets which are used for direct mapping to David
Cells (DCs) and (ii) local control nets for mapping to simple
The intermediate format is subsequently
passed to optimization tools and mapping tools where it is directly
mapped into asynchronous datapath and control circuits using David
Cells (DCs). Hardware components are selected from a basic library
for mapping. An RTL Verilog description can also be
output to a synthesis converter: i.e. a synchronous synthesis tool
(e.g. Synopsys Design Compiler) generates circuits which are converted
back to asynchronous circuits using a tool called Verimap.
Finally logic optimization tools are applied to generate
speed independent (SI) circuits.
A tool interface "VERISYN" has been developed for compiling and generating the
output nets together with a link for generating target outputs. Fig. 2. shows a screen dump
of the interface. The interface allows for Verilog specification entry, compilation, simulation and net generation,
viewing and a link is provided to mapping software. The interface has been written in C and uses a C++ graphics library. a download for this is provided below.
Fig. 2. Screen dump of "VERISYN" interface.
Asynchronous synthesis binary:
VERISYN Tool: verisyn.tar.gz (5.27MB)