Indie is a software tool which computes the smallest fully indicating implementation of a circuit.

Download and installation

The latest release of the tool can be found on Indie homepage:

The compilation of Indie tool from source is performed by the following command:

  $ make

This will compile a binary called indie. In order to start using the tool put this binary into a directory, which is referenced from the PATH environment variable (e.g. /usr/local/bin/). This can be done by running the following command as root:

  $ make install

If you already have an executable of the Indie tool, then just copy it into a directory which is referenced from your PATH environment variable.

Usage of the tool

Indie software tool aims to minimize the area overhead of an asynchronous implementation of any arbitrary Boolean circuit. It reads the structural net-list of a circuit in Verilog format and reports how each gate in the net-list can be mapped to certain type of functional module. The decision procedure is guided by the area cost of a particular technology which could be Delay-Insensitive-Minterm-Synthesis (DIMS) [1], Reduced Direct Logic (RDL) [2], Null Convention logic (NCL) [3], or the synthesized functional modules that can partially acknowledge different input combinations [4]. In the resulting implementation, at least one of the forks of each input and internal variable is partially acknowledged and the tool reports the status of a particular fork if it is partially acknowledged or not.

The detail list of Indie command line parameters and their meaning follows.

  -o,  --output OUTPUT_FILE_NAME   netlist output file [STDOUT]
  -i,  --include INC_FILE_NAMES    coma-separated library input files [STDIN]
  -p,  --property PRP_FILE_NAMES   coma-separated property input files [STDIN]
  -os, --otimisation-space IMPLEMENTATION_NAMES coma-separated implementation names
       used for optimisation (by default all available implementations are used)
  -gl, --greedy-layerwise          apply greedy layerwise heuristic
  -sl, --statistics-level[SL]      statistics level (SL=[0],1,2)
  -mi, --max-iteration[MI]         max nomber of iterations per region [1000000]
  -h,  --help                      print this help only
  -v,  --version                   print version only


  1. Jens Spars and Jrgen Staunstrup: "Delay-insensitive multi-ring structures". Integration, the VLSI journal, 15(3):313.340, October 1993.
  2. Christian D. Nielsen: "Evaluation of function blocks for asynchronous design". In Proc. European Design Automation Conference (EURODAC), pages 454-459. IEEE Computer Society Press, September 1994.
  3. Karl M.Fant: "Logically determined design - clockless system design with NULL Convention Logic". John Wiley & Sons, 2005.
  4. Y. Zhou, D. Sokolov, A. Yakovlev: "Cost-aware Synthesis of Asynchonous Datapath based on Partial Acknowledgement". NCL-EECE-MSD-TR-2006-113, Microelectronic System Design Group, School of EECE, University of Newcastle upon Tyne, February 2006.

Last modified 26/4/2006 by IGC