Smart computation circuits and systems for the EH context require the following elements:

1. Ability to sense the power and energy situation.
2. Circuits capable of working under variable energy and power supply.
3. Highly efficient and highly controllable power delivery, preferably on-chip.

This video describes some of the work going into these directions:

1. From voltage (Vdd) much of energy and power information can be derived. As a result we need on-chip voltage sensors with reasonable precision which themselves must operate under a variable power supply - the Vdd they are meant to sense. In other words, there cannot be any externally provided constant or dependable references, be they voltage, current, or time. We developed a number of solutions which all trace their references to internal physical characteristics of circuits or circuit components. These voltage sensors achieve reasonable precision and direct to code ability to simplify the computation. They consume very small amounts of energy and power, and have fast response times.
2. One crucial and basic infrastructure element of any computation system is the memory. Traditional memory does not work well under unpredictable and variable Vdd, and recovering from stoppages is very problematic. We designed the world's first truly self-timed SRAM which works across a large Vdd range and recovers from severe voltage losses without losing data.
3. An important aspect of the system design process is the ability to prototype before committing to ASIC solutions. FPGA provides this capability in the traditional design flow. Here we present an asynchronous FPGA structure which can work under variable Vdd and be tolerant to other circuit variability issues.
4. We investigated on-chip power delivery based on capacitors. By combining traditional SCC schemes used in DC-DC converters and simply arranged capacitor banks (CBB) we are able to tune the consumption and supply of energy by the computation system. This provides a flexible way of managing computation in response to energy availability or managing energy harvesting requests in response to computation needs.
5. The SRAM chip was eventually tested together with the HCBB power delivery system. Results confirm all analytical expectations.