LESTA - Logical-Effort-based Static Timing Analysis

LESTA stands for Logical-Effort-based Static Timing Analysis - "lesta" also is the female adjective for "quick" in Italian.

LESTA is a tool which, given an STG and its relative Verilog netlist, outputs the delay information for each input-to-output path of the STG. These delays are calculated using the Logical Effort method.
Alternatively the tool can calculate dthe delay information using characterised delay information. The tool requires a library file which contains the Logical Effort and characterised information for all the gates present in the Verilog netlist.

Download and installation

The tool is currently in its alpha release and can be obtained from the links below:

• Linux binaries
• Source code
• Example libraries
• Benchmarks

Installation instructions

Uninstallation instructions

Usage of the tool

The tool requires some files to be placed in a library directory. The installation creates a $HOME/lesta/lib directory for these files, but the path can be specified at runtime. These files are: - verilogLib.v: stub library of verilog modules used in the verilog netlist - leDelay.txt: text file containing the delay information for logical-effort - slopeDelay.txt: text file containing more accurate delay information

The tool is run using the following command:

lesta <libPath> <circuit>

• <libPath> indicates where the library files can be found
• <circuit> indicates the name of the circuit that is going to be used. The corresponding verilog file and STG file must have the same name <circuit> but different extension

Example:

(in the directory $HOME/lesta where the verilog and the STG file can be found)

test@test ~/lesta:> bin/lesta lib test

This implies that the library files are in $HOME/lesta/lib and the verilog and STG files are in $HOME/lesta. This directory will contain therefore a file "test.v" and a file "test.g"

The tool generates an output file which indicates all the possible input-to-output paths with their respective propagation delay for theoretical logical-effort calculation, characterised logical- effort, two levels of slope-based delay calculations.

Library files

The syntax of the library files is as follows:

VERILOG STUB FILE (verilogLib.v):

module <module>(<pin list>)
<input/output information>;
endmodule


This definition is repeated for all modules present

LOGICAL-EFFORT DELAY INFO (leDelay.txt)

For each gate:

d=tau(gh+p) => d=tau[g(Cout/Cin)+p]
tau*g = [(d1-d2)*Cin]/(Cout1-Cout2)
tau*p = d1-tau*g*h1
For the inverter, g = 1, so the formula for tau*g returns tau

begin[<gate name>]
<tab><pin name><tab><d1 rise><tab><d2 rise><tab><d1 fall><tab><d2 fall><tab><Cin><tab><le Cin><tab><g><tab><p>
end


SLOPE DELAY INFO (slopeDelay.txt)

This information are used to calculate the delay and the output slope of a gate given an input slope and the gate output load.
The formula is:

d = a*s*l + b*l + c*s + d

d is the delay
s is the input slope
l is the output load
a,b,c,d are the coefficients

A similar formula is used to calculate the output slope

begin[<gate name>]
#delay information
<tab><a rise><tab><b rise><tab><c rise><tab><d rise><tab><a fall><tab><b fall><tab><c fall><tab><d fall><tab><Capacitance>
#repeat for each pin

#slope information
<tab><a rise><tab><b rise><tab><c rise><tab><d rise><tab><a fall><tab><b fall><tab><c fall><tab><d fall><tab><Capacitance>
#repeat for each pin
end

Notes on the libraries provided

These example libraries only contain the logical effort delay information of a limited number of gates. These are enough to run the provided benchmarks.

For copyright reasons the characterised delay information of the gates are not available and have been set to zero.

To use the libraries, untar the file (we suggest into $HOME/lesta/lib)

Notes on the benchmarks

Please untar the file into a directory (we suggest into $HOME/lesta) and use the tool on the untar-ed files