TeLLA stands for TEsting of Low Latency Asynchronous circuits.

Download and installation

The tool is currently in its alpha release and can be obtained from the links below:

Usage of the tool

TeLLA is a tool for testing circuits obtained by direct mapping [1]. TeLLA reads in a verilog netlist and generates a set of test vectors required to test the circuit. The verilog netlist must be obtained using the OptiMist tool available at [ ]. Using the -t (testing) option in OptiMist a netlist including the test features can be obtained.

TeLLa provides a table consisting of a list of test vectors, it also consists information on the time required to apply one test vector to the circuit, total number of test vectors and the total time to apply all the test vectors.

Sample output of TeLLA:

SignalsTest sequences
tst_x_y0 1 1 1 1 1 1
tst_a_b1 0 1 1 1 1 1
in_02 2 0 2 2 2 2
in_10 0 0 0 0 0 0
out_01 1 1 1 0 1 1
out_13 3 3 3 3 0 3

Total number of control inputs = 2
Total number of test sequences = 7
Half-clock cycles required to apply one test sequence = 4
Total number of half-clock cycles to apply all test sequences = 28

Signals “tst_*” are the control inputs inserted to identify faults at the output. In test mode, each of these signals is set to 0 in each test sequence. At all other times it is set to 1.
The pseudo clock is applied to signals “in_*” and “out_*”. For these signals, numbers 0-3 in the table represent the clock pulses. These signals are also set to 0 in each test sequence.

Details of inserting the test features can be obtained from [2].

Command line parameters

Untar the binaries and the benchmarks

The tool can be run using the following command:
/PATH/tella /PATH/input_file(.v) stdout


  1. D.Sokolov, Automated synthesis of asynchronous circuits using direct mapping for control and data paths NCL-EECE-MSD-TR-2006-111, PhD Thesis, Microelectronic System Design Group, School of EECE, University of Newcastle upon Tyne, January 2006.
  2. D. Koppad, A. Bystrov, A. Yakovlev, Off-line Testing of Asynchronous circuits, 18th International Conference on VLSI Design, IEEE CS Press, Kolkata, January 3-7, 2005.

Last modified 9/6/2006 by IGC