Fourth UK Embedded Forum - Programme

Overview

The UK Embedded Forum is a workshop for UK-based PhD students working in the general area of embedded systems, which includes both hardware and software aspects, such as System-on-Chip design and Real-Time issues.

Deadlines

All papers are refereed by the programme committee. There is a size limit of 10 pages per submission, IET style. Presentation format is 30 minutes, including 5 minutes for questions and discussions. Authors are required to submit a pdf file electronically; please e-mail to albert.koelmans@ncl.ac.uk, no later than May 9th, 2008. Authors will be informed of the program committee's final decision by May 26th, 2008. The final version of the paper is due July 4th. As a result of the review process, authors may be asked to present a poster instead of giving a presentation.

Proceedings

Workshop proceedings will be published by IET as a digest. Instructions can be found at the IET web site. Papers must be original work, not under consideration elsewhere, and copyright will be assigned to IET. Papers will be made available in the IEEE digital library.

Submissions

Submissions are invited from individuals who are currently registered as PhD students at UK Universities. Topics include, but are not limited to:

embedded software design: predictable design methodologies, design with networked system environments, design space exploration
software/hardware and software/software codesign for embedded systems
hardware/software analysis, verification and test for embedded systems
embedded Linux and real-time Operating Systems
scheduling and WCET techniques for real-time systems
embedded System-on-Chip architectures
wireless techniques for embedded systems
novel embedded signal processing techniques
low power design for embedded systems
security design for embedded systems
interference and error tolerance
System-on-Chip techniques for embedded computing
novel I/O techniques and applications
System-level design
on-line and off-line testing techniques
Simulation techniques for embedded systems
Verification of embedded designs and tools
Benchmarking for embedded systems
Employment of DSPs in embedded systems
Data streaming and multimedia in embedded systems
Hardware/software support for real-time applications
Code transformation and program parallelization for embedded systems
Java-enabled devices
Case studies

Program Committee

Dr. I. Bate, University of York
Dr. L. Brackenbury, University of Manchester
Prof. A. Brown, University of Southampton
Dr. A. Bystrov, University of Newcastle upon Tyne
Dr. C. Clarke, Bath University
Dr. A. Koelmans, University of Newcastle upon Tyne
Dr. W. Luk, Imperial College
Dr. K. Maharatna, University of Southampton
Dr. K. McDonald-Maier, University of Essex
Dr. A. McEwan, University of Leicester
Dr. N. Nissanke, South Bank University
Dr. J. Nunez-Yanez, University of Bristol
Dr. M. Pont, University of Leicester
Dr. S. Sezer, Queen's University Belfast
Dr. M. Short, University of Leicester
Dr. T. Vladimirova, University of Surrey
Dr. R. Woods, Queen's University Belfast
Prof. M. Zwolinski, University of Southamption

Schedule

The general structure of the forum is shown below.

	Morning	Afternoon	Evening
9th September, 2008 (Tuesday)	travel	talks	dinner
10th September, 2008 (Wednesday)	talks	travel

Programme

Day 1 Tuesday, 9th September 2008
13.00	Registration
14.00	On the analogue approach to control a prosthetic hand E. Mangieri, A. Ahmadi, S. Ahmad, P. Chappell, University of Southampton
14.30	Towards Ctt (a programming language for time-triggered systems) D. Mearns, M. Pont and D. Ayavoo, University of Leicester
15.00	Stochastic Modeling Of Dynamic Power Management Policies And Analysis Of Their Power-Latency Tradeoffs Y. Chen, F. Xia, D. Shang, A. Yakovlev, University of Newcastle
15.30	Tea break
16.00	Towards increased Power Efficiency in low end embedded Processors: Can Cache help? M.Qadri, K. McDonald-Maier, University of Essex
16.30	Synchronising tasks in wireless multi-processor environments using a shared-clock architecture: A pilot study M.Amir, M. Pont, University of Leicester
17.00	Real-time Application Support for a Novel SoC Architecture M. Khan, J. Navaridas X. Jin, L. Plana, V. Woods and S. Furber, University of Manchester
17.30	Tuning protocols to improve the energy efficiency of sensornets J. Tate, I. Bate, S. Poulding, University of York
19.30	Forum Dinner
Day 2 Wednesday, 10th September 2008
09.00	A Novel Programmable Traffic Manager Design for Next Generation Networks Q. Zhang, A. Marshall, R. Woods, S. O'Neill, Queen's University Belfast
09.30	Hardware implementation of a shared-clock scheduling protocol for CAN: A pilot study. I. Sheikh, M. Short and M. Pont, University of Leicester
10.00	Hardware Typed Registers: Increasing Instruction Set Encoding Efficiency A. Robinson, University of Manchester
10.30	Coffee
11.00	Design and implementation of a static pre-emptive scheduler with highly-predictable behaviour H. Wang, M. Pont, University of Leicester
11.30	Deploying a time-triggered shared-clock architecture in a multiprocessor system-on-chip design K. Athaide, M. Pont and D. Ayavoo, University of Leicester
12.00	Implementing a simple but flexible time triggered architecture for practical deeply embedded applications M. Hanif, M. Pont, D. Ayavoo, University of Leicester
12.30	Close

Location

The workshop is held at the University of Southampton.

Registration and Accommodation

Registration form: here. Registration deadline: 4th August .

Accommodation is at the University, and is included in the price.

Contacts

Local organiser:

Koushik Maharatna

(km3@ecs.soton.ac.uk)

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