Fifth UK Embedded Forum - Programme
The UK Embedded Forum is a workshop for UK-based PhD students working in the general area of embedded systems, which includes both hardware and software aspects, such as System-on-Chip design and Real-Time issues.
All papers are refereed by the programme committee. There is a size limit of 10 pages per submission, IET style. Presentation format is 30 minutes, including 5 minutes for questions and discussions. Authors are required to submit a pdf file electronically; please e-mail to firstname.lastname@example.org, no later than May 9th, 2009. Authors will be informed of the program committee's final decision by May 26th, 2009. The final version of the paper is due July 10th. As a result of the review process, authors may be asked to present a poster instead of giving a presentation.
Submissions are invited from individuals who are currently registered as PhD students at UK Universities. Topics include, but are not limited to:
The general structure of the forum is shown below.
|23rd September, 2009 (Wednesday)||travel||talks||dinner|
|24th September, 2009 (Thursday)||talks||travel|
|Day 1 Wednesday, 23rd September 2009|
|14.00||Verification of Generated VHDL Systems S. Wood, D. Akehurst, G. Howells, K. McDonald-Maier, University of Kent, University of Essex|
|14.30||Accelerating CMOS Device Model Evaluation Using Multi-FPGA Systems A. Maache, J. Reeve, M. Zwolinski, University of Southampton|
|15.00||A Generic and Accurate RTOS-centric Embedded System Modelling and Simulation Framework K. Yu, N. Audsley, University of York|
|16.00||Flexible Motion Estimation Processors for High Definition Video Coding T. Spiteri, G. Vafiadis, J. Nunez-Yanez, University of Bristol|
|16.30||A novel shared-clock algorithm for CAN-based networks with a star topology M. Amir, M. Pont, University of Leicester|
|17.00||An Evaluation of Asynchronous Architecture for System Level Power Reduction G. Ndu, J. Garside, University of Manchester|
|17.30||Introduction to Conditional Partial Order Graphs A. Mokhov, A. Yakovlev, Newcastle University|
|Day 2 Thursday, 24th September 2009|
|09.00||Supporting the migration from event triggered to time triggered architectures using design patterns F. Lakhani, A. Das, M. Pont, University of Leicester, TTE Systems Ltd|
|09.30||Monte Carlo Static Timing Analysis: Assessing Stochastic Process Variations At The Circuit Level M. Merrett, M. Zwolinski, University of Southampton|
|10.00||Dual Rate CAN Controller I. Sheikh, M. Short, University of Leicester|
|11.00||Deadlock free resource sharing using TTH scheduler in a novel FPGA based embedded processor S. Rizvi, M. Pont, University of Leicester|
|11.30||A novel remote debugging system for reliable embedded systems N. Ahmad, M. Pont, University of Leicester|
The workshop is held at the University of Leicester.
The event will take place in the Department of Engineering, University
Leicester (the "Engineering Tower", 4th floor). Maps are
Those who have booked accommodation will be staying in the Ibis Hotel.
Where possible, travel by rail is recommended (the hotel is a few minutes walk from Leicester station: the University campus is around 20 mins walk from Leicester station / the hotel).
The registration fee is 80 pounds, including one night bed and breakfast, the workshop dinner, and printed proceedings.
|Local organiser:||Michael Pont||(email@example.com)|