WORKSHOP DESCRIPTION

There is increasing interest in the problem of communication between digital systems which are asynchronous, or do not share a common clock. Implementations of systems on sub-micron integrated circuits are likely to have this characteristic, since it is becoming difficult to distribute a single clock over the entire chip with an acceptable skew.

From the ITRS (International Technology Roadmap for Semiconductors) website, (http://public.itrs.net/), communications-centric design is listed as one of the design challenges. "... As it becomes impossible to move signals across a large die within one clock cycle or in a power-effective manner, or to run control and dataflow processes at the same clock rate, the likely result is a shift to asynchronous (or, globally asynchronous and locally synchronous (GALS)) design style. ...".

In systems where the distribution of a single clock is either impossible, such as a ground-based missile control system with some processors in the missile and some processors on the ground, or impractical, as, for example, in a one billion transistor chip, data must be exchanged between one or more independently/heterogeneously timed subsystems. This can lead to problems of data coherence, throughput, and timeliness, which must be considered in the design of the interface. Design of a reliable asynchronous interface requires an understanding of the issues of metastability, which can result in data items being incompletely transmitted, and hence becoming incoherent, and of asynchronous circuit design, to enable reliable and speed independent interface control circuits to be achieved, with an acceptable power dissipation and throughput. Both of these topics are circuit design issues, which have a considerable impact on the interface design and performance. The elimination of the need to distribute a single high-power clock or a set of sychronised clocks, can also have beneficial effects in the reduction of electromagnetic radiation, and so improve the electromagnetic compatibility.

The aim of the workshop is to bring together researchers and practitioners with interests in (but not limited to):

The format will be regular (30 min) and short (15 min) presentations on the problem spaces, industrial experiences, and posters of work in progress, with some invited speakers from companies and research groups active in this subject area.

The workshop should be of interest to those involved in the design of asynchronous and high performance multiply-clocked systems, as well as those involved in digital circuit design, and design tools for sub-micron circuits and systems-on-chip.

Selected papers will be invited for publication in an extended form in a special issue of the Wiley Circuit Theory and Applications Journal on 'Circuits for Asynchronous Interfacing'.