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Two-day workshop on

Asynchronous INTerfaces: tools, techniques, and implementations
Previously hosted at:

TU Delft, The Netherlands

19-20th July 2000

Supported by
IEEE Circuits and Systems Society
IEEE Circuits and Systems Benelux Chapter &
United Kingdom and Republic of Ireland Circuits and Systems Chapter


There is increasing interest in the problem of communication between digital systems which are asynchronous, or do not share a common clock. Implementations of systems on sub-micron integrated circuits are likely to have this characteristic, since it is becoming difficult to distribute a single clock over the entire chip with an acceptable skew.

In systems where the distribution of a single clock is either impossible, such as a ground-based missile control system with some processors in the missile and some processors on the ground, or impractical, as, for example, in a one billion transistor chip, data must be exchanged between one or more independently timed subsystems. This can lead to problems of data coherence, throughput, and timeliness, which must be considered in the design of the interface. Design of a reliable asynchronous interface requires an understanding of the issues of metastability, which can result in data items being incompletely transmitted, and hence becoming incoherent, and of asynchronous circuit design, to enable reliable and speed independent interface control circuits to be achieved, with an acceptable power dissipation and throughput. Both of these topics are circuit design issues, which have a considerable impact on the interface design and performance. The elimination of the need to distribute a single high-power clock or a set of sychronised clocks, can also have beneficial effects in the reduction of electromagnetic radiation, and so improve the electromagnetic compatibility.

The aim of the workshop is to bring together researchers and practitioners with interests in (but not limited to):

  • High performance interfaces: synchronous and/or asynchronous.
  • The impact of the new deep submicron technologies (0.18 micron and below) on interfacing.
  • Synchronising (sub)systems with very large clock skew.
  • Distributed clocking.
  • Reliable and robust communication mechanisms and interface control circuits.
  • Methods and tools for interface modelling and design.

The format will be regular (30 min) and short (15 min) presentations on the problem spaces, industrial experiences, and posters of work in progress, with some invited speakers from companies and research groups active in this subject area.

The workshop should be of interest to those involved in the design of asynchronous and high performance multiply-clocked systems, as well as those involved in digital circuit design, and design tools for sub-micron circuits and systems-on-chip.

    • Damal Arvind (University of Edinburgh, UK)
    • Eric Campbell (Matra BAe Systems, UK)
    • Eduard Cerny (Universite de Montreal, Canada)
    • Tony Davies (King’s College, University of London, UK)
    • Steve Furber (University of Manchester, UK)
    • Mark Greenstreet (University of British Columbia, Canada)
    • David Harris (Harvey Mudd College, USA)
    • David Kinniment (University of Newcastle-upon-Tyne, UK)
    • Prabhakar Kudva (IBM, USA)
    • Luciano Lavagno (Universita' di Udine, Italy)
    • Ad Peeters (Philips Research, Eindhoven, The Netherlands)
    • Christian Piguet (CSEM, Switzerland)
    • Ken Stevens (Intel, Oregon, USA)
    • Alex Yakovlev (University of Newcastle-upon-Tyne, UK)

    Day 1: Wednesday 19 July 2000
    8:30-9:15 Registration
    9:15-9:30 Welcome (Prof. Dr. Ir. J. van Katwijk, ITS Faculty Dean)
    Session 1: High Level Aspects of Interfacing
    9:30-10:30 H. Simpson and E. Campbell (Invited Lecture) - Real-Time network architecture: principles and practice
    10:30-11:00 Coffee
    11:00-11:30 S. P. Tyerman and P. J. Ashenden - High Level Synthesis of Asynchronous Digital Systems
    11:30-12:00 G. Birtwistle and M. Morley - Specification and property checking of control circuits of TK, an asynchronous AMULET-like processor
    12:00-12:30 I.G. Clark and A.C. Davies - A comparison of some wait-free communication mechanisms
    12:30-14:00 Lunch
    Session 2: Interface Design Techniques
    14:00-15:00 J. Cortadella (Invited Lecture) - Automatic Synthesis and Verification of Asynchronous Interface Controllers
    15:00-15:30 S. Delong, F. Xia and A. Yakovlev - An implementation of a three-slot asynchronous communication mechanism using self-timed circuits
    15:30-16:00 G. Birtwistle - Control states in asynchronous pipelines
    16:00-16:30 Coffee
    16:30-17:00 A. Peeters - Support for interface design in Tangram
    17:00-17:30 N. Starodoubtsev, M. Goncharov, I. Klotchkov and A. Smirnov - Synthesis of asynchronous interface circuits by STG refinement
    17:30-18:00 D. Furey and M.B. Josephs - Delay Insensitive interface specification
    18:00-18:30 Discussion
    Day 2: Thursday 20 July 2000
    Session 3: Synchronisation and Arbitration
    9:00-10:00 C. Dike (Invited Lecture) - Advances in Metastability Theory and Application
    10:00-10:30 R. Ginosar and R. Kol - Adaptive synchronization
    10:30-11:00 Coffee
    11:00-11:30 C. Piguet - Robustnes of asynchronous sequential standard cells in a synchronous environment
    11:30-12:00 M. Renaudin and J.B. Rigaud - Modelling and design/synthesis of arbitration problems
    12:00-12:30 S.W. Moore, G.S. Taylor, P.A. Cunningham, R.D. Mullins and P. Robinson - Interfacing asynchronous and synchronous subsystems
    12:30-14:00 Lunch
    Session 4: Synchronisation and Communication
    14:00-15:00 S. Schuster (Invited Lecture) - Low Power Asynchronous Interlocked Pipelined CMOS (IPCMOS) Circuits Operating at 3.3 -4.5 GHz
    15:00-15:30 S.B. Furber, A. Efthymiou and Montek Singh - A power-efficient duplex communication system
    15:30-16:00 D.K. Arvind and Kristian Hildingsson - Power Tradeoffs in Asynchronous Interfaces
    16:00-16:30 Discussion and close

  • Workshop materials will be distributed at the workshop.

    If this workshop is of interest to you then please register your interest, give feedback, or request more information here.


Last modified 4/9/2000 by IGC