Async 2008 & NoCS 2008 Programme

	Mon (7th)	Tue (8th)	Wed (9th)	Thu (10th)	Fri (11th)
8:00		Registration + Official Open
8:30	Registration	Keynote Async-1	Keynote NoCS-1	Keynote Async-2	Keynote NoCS-2
9:00	Tutorial David Kinniment (1)
9:30		Async-1	NoCS-3	Async-3	NoCS-6
10:00
10:30	Coffee + Tutorial Demo 1	Coffee	Coffee	Coffee	Coffee
11:00	Tutorial David Kinniment (2)	Async-2	NoCS-4	Async-4	NoCS-7
11:30
12:00	Tutorial Demo 2				NoCS-8 Poster Session + Demos
12:30	Lunch
13:00		Lunch	Excursion to Beamish Open Air Museum light lunch included	Lunch	Lunch
13:30	Tutorial Sachin Sapatnekar
14:00				NoCS-5	Panel
14:30		NoCS-1
15:00					Close
15:30	Coffee + Tutorial Demo 3			Coffee
16:00	Tutorial Mike Kishinevsky	Coffee		Async-5
16:30		NoCS-2
17:00
17:30	Tutorial Demo 4			Best Paper Award
18:00	Registration	Industrial Demos & Reception
19:00	Welcome Reception		Banquet

• Official Opening Tuesday 8th 08:15-08:30
  Welcome from Newcastle University Pro-Vice Chancellor, Professor Oliver Hinton.
  Welcome from General Chairs, Alex Yakovlev and John Bainbridge
  ASYNC PC Chairs, Jordi Cortadella and Alexander Taubin
  NOCS PC Chairs, Davide Bertozzi and Kees Goossens

Async-1: Data-driven asynchronous circuits
Chair: Jordi Cortadella

• Automatic Compilation of Data-Driven Circuits
  Doug Edwards, Sam Taylor and Luis Plana (09:30-10:00)
• Concurrency-Enhancing Transformations for Asynchronous Behavioral Specifications: A Data-Driven Approach
  John Hansen and Montek Singh (10:00-10:30)

Async-2: Variability, power and nanoelectronics
Chair: John Bainbridge

• High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators
  Jérémie Hamon, Laurent Fesquet, Benoît Miscopein and Marc Renaudin (11:00-11:30)
• Adapting Synchronizers to the Effects of On Chip Variability
  Jun Zhou, David Kinniment, Gordon Russell and Alex Yakovlev (11:30-12:00)
• Automatic Power regulation based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction
  Yvain Thonnart, Edith Beigne, Alexandre Valentian and Pascal Vivet (12:00-12:30)
• Asynchronous Nano-electronics: Preliminary Investigation
  Alain J. Martin and Piyush Prakash, Caltech (12:30-13:00)

Async-3: Latch protocols and pipelines
Chair: David Bormann

• The family of 4-phase latch protocols
  Graham Birtwistle and Kenneth Stevens (09:30-10:00)
• Heterogeneous Latch-based Asynchronous Pipelines
  Girish Venkataramani, Tiberiu Chelcea and Seth Goldstein (10:00-10:30)

Async-4: Efficient and reliable schemes for computation and communication
Chair: Jim Garside

• Block-Level Relaxation for Timing-Robust Asynchronous Circuits Based on Eager Evaluation
  Cheoljoo Jeong and Steven Nowick, Columbia University (11:00-11:30)
• Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic
  Tsung-Te Liu, Louis Alarcón, Matthew Pierson and Jan Rabaey (11:30-12:00)
• A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication
  Peggy McGee, Melinda Agyekum, Moustafa Mohamed and Steven Nowick (12:00-12:30)
• FPGA Implementation of an Asynchronous Processor with Online and Offline Testing Capabilities
  Nikolaos Minas, Matthew Marshall, Gordon Russell and Alex Yakovlev (12:30-13:00)

Async-5: Synthesis and verification of asynchronous controllers
Chair: Luciano Lavagno

• Derivation of Monotonic Covers for Standard-C Implementation Using STG Unfoldings
  Victor Khomenko, Newcastle University (16:00-16:30)
• Coping with Soft Errors in Asynchronous Burst-Mode Machines
  Sobeeh Almukhaizim, Feng Shi and Yiorgos Makris (16:30-17:00)
• Automated verification of asynchronous circuits using circuit Petri nets
  Ivan Poliakov, Andrey Mokhov, Ashur Rafiev, Danil Sokolov and Alex Yakovlev (17:00-17:30)

NoCS-1: TUNING NOC ARCHITECTURE FOR SPECIFIC PURPOSES
Chair: Ran Ginosar

• The papers presented in this session show how network building blocks or an entire architecture can be optimized for specific purposes, such as debugging, fault-tolerance, or low power.
• Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
  Bart Vermeulen, Kees Goossens and Siddharth Umrani (14:30-15:00)
• A Lightweight Fault-tolerant Mechanism for Network-on-chip
  Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano and Timothy Pinkston (15:00-15:30)
• Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
  Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang and Hideharu Amano (15:30-16:00)

NoCS-2: FPGA-BASED AND RECONFIGURABLE NOC DESIGN
Chair: Davide Bertozzi

• The papers in this session extend FPGAs with networks on chip techniques, or conversely, networks are augmented with circuit-switching techniques around the routers.
• A Network of Time-Division Multiplexed Wiring for FPGAs
  Rosemary Francis, Simon Moore and Robert Mullins (16:30-17:00)
• Hardwired Networks on Chip in FPGAs to unify Functional and Configuration Interconnects
  Kees Goossens, Martijn Bennebroek, Jae Young Hur and Muhammad Aqeel Wahlah (17:00-17:30)
• ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
  Mikkel B. Stensgaard and Jens Sparsř (17:30-18:00)

NoCS-3: LOW-POWER AND RELIABLE LINK DESIGN
Chair: Marcello Lajolo

• The papers in this session present link design techniques trading off power with reliability.
• SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks
  Alireza Ejlali and Bashir M Al-Hashimi (09:30-10:00)
• Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip
  Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang and Wei Hwang (10:00-10:30)

NoCS-4: TOPOLOGY AND ROUTING DESIGN: methodologies and tools
Chair: Andreas Hansson

• Topology and routing design require high-level exploration tools and methodologies and an interaction of these latter with physical synthesis tools. All these issues are covered by the papers presented in this session.
• An Efficient Implementation of Distributed Routing Algorithms for NoCs
  José Flich, Samuel Rodrigo and José Duato (11:00-11:30)
• Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms
  Maurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar and Vincenzo Catania (11:30-12:00)
• Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework
  Francisco Gilabert, Simone Medardoni, Davide Bertozzi, Luca Benini, Maria Engracia Gomez, Pedro Lopez and Jose Duato (12:00-12:30)
• Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
  Bin Li, Li-Shiuan Peh and Priyadarsan Patra (12:30-13:00)

NoCS-5: GALS NOC IMPLEMENTATION
Chair: Jens Sparsř

• GALS NoC design is addressed at different levels of abstraction in this session. Proposed papers range form comprehensive system-wide implementation and design choices to design-for-test implementation for asynchronous interconnects.
• Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
  Edith Beigné, Fabien Clermidy, Sylvain Miermont and Pascal Vivet (14:00-14:30)
• Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture
  Ivan Miro Panades, Fabien Clermidy, Pascal Vivet and Alain Greiner (14:30-15:00)
• A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application
  Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle and Chantal Robach (15:00-15:30)

NoCS-6: QUALITY OF SERVICE
Chair: Kees Goossens

• The papers in this session discuss NoC performance and quality of service.
• Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
  Zheng Shi and Alan Burns
  (09:30-10:00)
• Statistical Approach to NoC Design
  Itamar Cohen, Ori Rottenstreich and Isaac Keslassy (10:00-10:30)

NoCS-7: COHERENCE REQUIREMENTS ON THE INTERCONNECT
Chair: Federico Angiolini

• The coherence protocol in CMP systems poses requirements on the system interconnect which have to be met through proper architecture design choices, as described by the papers in this session.
• Reducing the Interconnection Network cost of Chip Multiprocessors
  Pablo Abad, Valentin Puente and Jose Angel Gregorio (11:00-11:30)
• Circuit-Switched Coherence
  Natalie Enright Jerger, Li-Shiuan Peh and Mikko Lipasti (11:30-12:00)

NoCS-8: POSTER SESSION
Chair: Kees Goossens

• Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-recursive network
  Suboh Suboh, Mohamed Bakhouya and Tarek El-Ghazawi
• Low-cost VC allocator design for virtual channel wormhole routers in networks-on-chip
  Min Zhang and Chiu-Sing Choy
• Network Simplicity for Latency Insensitive Cores
  Daniel Gebhardt and Kenneth Stevens
• Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
  Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens and Marco Bekooij
• Analysis and Design of Wave-Pipelined Global Interconnects in FPGAs
  Terrence Mak, Crescenzo D'Alessandro, Pete Sedcole, Peter Y.K. Cheung, Alex Yakovlev and Wayne Luk
• An on-Chip and inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator
  Luis Plana, John Bainbridge, Steve Furber, Yebin Shi and Jian Wu
• Dual-channel access mechanism for cost-effective NoC design
  Shijun Lin, Li Su, Depeng Jin and Lieguang Zeng

Best Paper Award
Chair: Jens Sparsoe

• 17:30-17:45