High Level Asynchronous Synthesis Toolkit

(Petri nets to David Cell Hardware Circuit – PN2DCs)

Our research centres around the implementation of a new CAD tool set for generating asynchronous circuits from high-level language level-sensitive specifications. Compared to synchronous CAD tools, which are very mature and accepted by industry, there is still a shortage of mature CAD tools to support asynchronous circuit designs. We present supporting tools here which are targeted towards bridging this gap.

One of the reasons for the lack of commercial tools is the level of complexity of generating complex asynchronous circuits. Global asynchronous control solutions are error prone and suffer from state explosion problems. Direct mapping approaches attempt overcome this by using handshake specifications which describe the control and datapath together. Here, we adopt a global direct mapping approach for input commercial language specifications which covers direct asynchronous mapping at all levels of the synthesis flow.

Our aim is to avoid the state explosion problem inherent in other asynchronous tools such as Petrify by using a synthesis approach which combines the advantages of using a direct mapping method and using a commercial language such as Verilog (VHDL) as a specification language. We explore the design using high level synthesis, making use of a direct mapping approach from an intermediate Petri net format to generate asynchronous speed independent implementations.

This toolkit consists of two parts. One is verisyn tool (, and the other one is pn2dcs tool. The verisyn tool is used to compile and convert high-level commercial language descriptions e.g. Verilog (VHDL) into a novel intermediate Petri-net format. The pn2dcs tool is used to direct-map the intermediate format to asynchronous circuits. For more details about the pn2dcs tool please read the documents in the tool package below.

Asynchronous synthesis software:

PN2DCs tool package: pro-pn2dcs.tar.gz (180KB)

Last modified 9/12/2004 by IGC