NoC 2006

http://async.org.uk/noc2006

Registration: Go to DATE 2006 registration site and select either the entire conference or Friday Workshop W2.

Accommodation: Go to DATE 2006 accommodation site.

Advances in semiconductor technology, design re-use and tools are enabling designers to put complex, massively parallel multiprocessor systems on a single chip. The idea of packet-switching Networks on a Chip (NoC) offers more flexibility, robustness and better resource utilisation than what is provided by traditional bus-based architectures. NoCs are poised to be an alternative to buses, but should they rather be seen complementary than alternative in the longer term? What kind of new communication paradigms and signaling schemes are more suited for NoCs in order to battle inherent signal integrity and soft errors? Are there fundamental issues about on-chip interconnects that will limit performance and dependability of communication as Moore's Law gradually runs out of steam within the next decade? What about new technologies such as optical interconnects?

These and other questions will be in the centre of this workshop, which will bring together researchers actively working on future interconnects and NoCs. The workshop is also keen to invite hardware and system engineers interested in new developments in this area. In a final panel, experts in the field will address the challenges and opportunities for on-chip interconnect paradigms and project their vision on the current developments in academic and industrial research.

The workshop will serve to launch a new series of high quality symposia, targetted at Networks on Chip and Interconnects. The need for such a dedicated forum is increasingly recognised due to the steady growth in research activity and contributions that are currently spread over multiple conferences in diverse areas such as architecture, circuits, CAD and networking. It will also provide an excellent thematic framework for interaction between industry and academia.

Links:

Workshop Goal
To discuss problems and opportunities, present points of view and develop collective vision for the future of on-chip interconnects and communications
To survey research by the leading research groups working in this area around the world
To plan a new international symposium on NoCs and interconnects.

Workshop Program

08:30	Welcome and Introduction
08:45-09:15	Keynote: NoCs: Vision, reality, trends Luca Benini, DEIS - Bologna U, Italy
09:20-10:00	Session 1: Advances in NoCs (invited presentations) Chair: Ran Ginosar, Technion, Israel Standards in NoC: What can we gain? Axel Jantsch, KTH Stockholm, Sweden · Networks and Applications: Are Application-Specific Networks Worth the Trouble? Wayne Wolf, Princeton U, United States
10:00-10:20	BREAK
10:20-11:00	Session 2: Advances in On-Chip Interconnects (invited presentations) Chair: Pol Marchal, IMEC, Belgium On-Chip Interconnect: The past, present, and future Eby Friedman, U of Rochester, United States · Potential impact of emerging System-in-Packaging technologies on system design Eric Beyne, IMEC, Belgium
11:00-12:00	Introducing Research Groups Chair: Avinoam Kolodny, Technion, Israel Presenters: John Bainbridge, Silistix, United Kingdom Israel Cidon, Technion, Israe Marcello Coppola, ST Microelectronics, France Shinobu Fujita, Toshiba, Japan Kees Goossens, Philips Research, The Netherlands Graham Hellestrand, VaST Systems, United States Andre Ivanov, UBC, Canada Shashi Kumar, Jönköping U, Sweden Philippe Martin, Arteris, France Radu Marculescu, CMU, United States Jari Nurmi, Tampere U. Tech., Finland Ian O’Connor, LEOM, France Christer Svensson, Linköping U, Sweden Hoi-Jun Yoo, KAIST, Korea
12:00-13:00	LUNCH
13:00-14:30	Poster Session Poster Abstracts This session will enable direct interactions among all researchers. Its goals are to get to know each other and each other's work, and to create opportunities for research collaborations. “EEG Biomedical Sensors Network on Chip (EBSNOC)” M. Saleh and Axel Jantsch Royal Institute of Technology (KTH), Sweden *“Evaluation of On-chip Networks Using Deflection* Routing”** Z. Lu, M. Zhong and A. Jantsch Royal Institute of Technology, Sweden “Utilizing NoC Switches as BIST-structures in 2D Mesh Network-on-Chip” K. Petersén¹, J. Öberg¹, S. Evain² and J. Diguet² ¹Royal Institute of Technology (KTH), Sweden ² University of South Brittany, France “Emerging Networks on Chip: Lessons Learned to Win the Future” I. Al Khatib Royal Institute of Technology, , Sweden “Interoperability Protocol and Algorithms for Network-on-Chip Autonomous-System Communications for the Next Generation Biomedical Sensor-Networks” I. Al Khatib¹, A. Jantsch¹, R. Nabiev² and L. O. Alima³ ¹ Royal Institute of Technology, Sweden ² Karolinska University Hospital Huddinge, Sweden ³ Université de Mons-Hainaut, Belgium “Synchronous Latency Insensitive Design in Æthereal NoC “ X. Ru¹, J. Dielissen², C. Svensson³and K. Goossens² ¹ Philips Semiconductors, Switzerland ² Philips Research, The Netherlands 3 Linköping University, Sweden “An improved method for delay fault testing of NoC interconnections” T. Bengtsson¹, S. Kumar¹, A. Jutman² and R. Ubar² ¹ Jönköping University, Sweden ² Tallinn University of Technology, Estonia “STAR : An Efficient Routing Strategy for NoC with Mixed QoS Requirements” D. Andreasson and S. Kumar Jönköping University, Sweden “On Options for Accessing Regions in NoC” R. Holsmark and S. Kumar Jönköping University, Sweden “Application Parallelism Exploitation using NoC with Multithreaded Processors” R. Pop and S. Kumar Jönköping University, Sweden “Versatile XGFT Network-On-Chip with Improved Fault-Tolerance for Multi-Processor Systems-on-Chip” H, Kariniemi and J. Nurmi Tampere University of Technology, Finland “Fault-Diagnosis-And-Repair System for Improving the Fault-Tolerance and Manufacturability of MPSoCs“ H. Kariniemi and J. Nurmi Tampere University of Technology, Finland “Exploration of CDMA-Based Network-on-Chip” X. Wang and J. Nurmi Tampere University of Technology, Finland “NoC-Based Platform Implementation on FPGA” T. Ahonen, J. Kylliäinen, C. Brunelli and Jari Nurmi Tampere University of Technology, Finland “A Hierarchical Approach to Network-on-Chip” T. Ahonen and J. Nurmi Tampere University of Technology, Finland “PROTEO – A Flexible Network-on-Chip Scheme” T. Ahonen, D. Sigüenza-Tortosa * and J. Nurmi Tampere University of Technology, Finland * Complutense University of Madrid, Spain “SystemC Simulation Model of a Flexible Network-on-Chip” S. Määttä and J. Nurmi Tampere University of Technology, Finland “Network-on-Chip Generation and Optimization Tool” T. Ahonen, H. Bin and J. Nurmi Tampere University of Technology, Finland “FAUST, an Asynchronous Network-on-Chip based Architecture for Telecom Applications” P. Vivet, F. Clermidy, D. Lattard CEA-LETI France “Heterogeneous integration of light sources on an SOI waveguide platform for photonic interconnects on CMOS (PICMOS)” G. Roelkens1, J. Van Campenhout1, D. Van Thourhout1, R. Baets1, P. Rojo-Romeo2, C. Seassal2, P. Regreny2, P. Viktorovitch2, I. O’Connor2, L. Di Cioccio3 and J. Fedeli3 ¹Ghent University Belgium ²Ecole Centrale de Lyon France ³CEA-DRT/LETI France “Optical interconnect for on-chip data communication” I. O’Connor¹, F. Tissafi-Drissi¹, D. Navarro¹, F. Mieyeville¹, F. Gaffiot¹, J. Dambre², M. De Wilde², D. Stroobandt² and D. Van Thourhout³ ¹ Ecole Centrale de Lyon, France ² Ghent University, Belgium ³ IMEC / Ghent University, Belgium “Methodology, benefits and tools for NoC topology exploration” P. Martin and J. Lecler Arteris SA, France “µSpider NoC Road Map” S. Evain and J. Diguet, University of South Brittany, France “Modeling and synthesis of Asynchronous Network on Chip using SystemC” C. Koch-Hofer and M. Renaudin TIMA, France “STNoC™: An Evolution Towards MPSoC Era” M. Coppola¹, C. Pistritto², R. Locatelli¹ and Alberto Scndurra² ¹ STM, AST Grenoble Lab, France ² STM, HPC, Italy “Design of a simple clockless Network-on-Chip for an audio DSP chip” M. Stensgaard¹, T. Bjerregaard¹, J. Sparsø¹ and J. Pedersen² ¹ Technical University of Denmark (DTU) ² William Demant Holding “Clockless On-Chip Networks and MANGO” T. Bjerregaard, J. Sparsø and M. Stensgaard Technical University of Denmark, Denmark “Multiple-rail phase-encoding for NoC” C. D'Alessandro¹, D. Shang¹, A. Bystrov¹, A. Yakovlev¹, O. Maevsky ² ¹ University of Newcastle upon Tyne, UK ² Intel Labs, Moscow “Design of fast and reliable synchronisers for NoCs “ J. Zhou, D. Kinniment, G. Russell, and A. Yakovlev University of Newcastle upon Tyne, UK “CHAINworks™ – an EDA tool suite and IP libraries for self-timed interconnect design synthesis” J. Bainbridge, A. Bardsley and R. McGuffin, Silistix, United Kingdom “Towards a Communication-Centric Design Methodology” A. Banerjee, R. Francis, J. Lee, J. May, S. W. Moore and R. D. Mullins Computer Laboratory, University of Cambridge, United Kingdom “BIST for NoC Interconnects” C. Grecu¹1, P. Pande², A. Ivanov¹ and R. Saleh¹ ¹ University of British Columbia, Canada; ² Washington State University, United States “A Distributed, Interleaved FIFO for SoC Interconnect” S. Sood, M. Greenstreet and R. Saleh University of British Columbia “Clock Synchronization in NoCs using Distributed FIFOs” P. Pande and J. Nyathi Washington State University, United States “A 20Gb/s Transceiver for Network-On-Chip” Z. Asgar, J. Zou, P. Jain, R. Kamath and R. Harjani University of Minnesota, United States “Constraint-Driven Communication Synthesis of Networks On-Chip” A. Pinto, L.P. Carloni and A.L. Sangiovanni-Vincentelli U.C. Berkeley, United States Columbia University, United States “Application-Specific Networks-on-Chips” J. Xu and W. Wolf Princeton University, United States “Introduction to the Princeton Polaris Project” V. Soteriou, N. Eisley, H. Wang, B. Li and L. Peh Princeton University, United States “NoC Performance Optimization via Long-range Link Insertion” U. Ogras and R. Marculescu Carnegie Mellon University, United States “Performance Enhancement through Early Release and Buffer Optimization in Network-on-Chip Router Architectures” J. Kim D. Park C. Nicopoulos N. Vijaykrishnan and C. Das The Pennsylvania State University, United States “Empirical Optimization of Multiprocessor Systems and their Heterogeneous Communication Fabrics” G. Hellestrand, J. Torossian and C. Alford VaST Systems, United States “Spatial Division Multiplexing: A Novel Approach for Guaranteed Throughput on NoCs” A. Leroy^1/2, P.Marchal¹, F. Robert ² and F. Catthoor^1/3 ¹ IMEC Belgium ² VUB Belgium ³KUL Belgium “A Flexible System Level Design Methodology Applied to NoC” A. Vander Biest, A. Leroy and F. Robert ULB Belgium “Extended Global Interconnect Architecture for Nano-CMOS Technologies” J.Balachandran¹, S.Brebels¹, G.Carchon¹, M.Kuijk², W.De Raedt¹, B.Nauwelaers ³ and E.Beyne¹, ¹ IMEC Belgium ² VUB Belgium ³ KUL Belgium “Dynamic Time-Slot Allocation for Networks on Chip with TDMA QoS” T. Marescaux¹, B. Brick´e^1,2, P. Debacker^1,2, V. Nollet¹, H. Corporaal³ ¹IMEC V.Z.W., Belgium ²Katholieke Universiteit Leuven, Belgium ³Technical University Eindhoven ( TU/e ), The Netherlands “Reconfigurable Optical Networks for On-Chip Multiprocessors” W. Heirman^a, J. Dambre^a, I. O’Connor^b, J. Van Campenhout^a ^aELIS, Ghent University, Belgium; ^bLEOM, Ecole Centrale de Lyon, France “Introduction to KAIST BONE project” K. Lee, S. Lee, D. Kim, K. Kim, J. Kim and H. Yoo Korea Adv. Inst. of Science and Technology (KAIST), Korea “Novel Performance of Three-dimensional (3D) On-chip Crossbar Bus using non-Silicon Transistors” S. Fujita^1/2, K. Abe¹, K. Nomura¹ and T. Lee³, ¹Frontier Research Laboratory, Toshiba, Kawasaki, Japan ² Toshiba America Research, United States ³ Stanford University, United States “Dynamic Multi-grain Pipelined Interconnect” M. Imai, T. Azuma, K. Watanabe and T. Nanya Res. Ctr for Adv. Sci. and Tech., The U. of Tokyo, Japan “QoS Oriented Configurable Network on Chip” M. Al Faruque, X. Ye, G. Weiss and J. Henkel University of Karlsruhe, Germany “A Lightweight NoC for the NOVA Packet Processing Platform” C. Sauer¹, M. Gries¹, S. Dirk¹, J.-C. Niemann², M. Porrmann², U. Rückert² ¹Infineon Technologies, Germany ² HNI Paderborn, Germany “A dedicated communication layer for Power Management of NoC based SoCs” N. Genko¹, D. Atienza^1/2, A. Aquaviva¹ and G. De Micheli¹ ¹ EPFL, Switzerland ² DACYA/UCM, Spain. “HW/SW Partitioning and Interface Synthesis in NoCs” F. Regazzoni and M. Lajolo ALaRI - USI, Lugano, Switzerland NEC Laboratories America, Princeton, United States “Recovering from Transient Memory Failures in NoC Designs by Software Data Restore” F. Angiolini, D. Atienzaz, S. Murali, L. Benini, G. De Micheli DEIS, University of Bologna, 40136 Bologna, Italy “Buffer output capacitance effect on NoC line drivers performance” G. Cappuccino, A. Pugliese, G. Cocorullo DEIS-University of Calabria, Italy “QNoC: QoS Network on Chip” E. Bolotin, I.Cidon, R. Ginosar and A.Kolodny Electrical Engineering Department, Technion, Haifa, Israel “Efficient Link Capacity and QoS Design for Network-on-Chip” Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny Electrical Engineering Department, Technion, Haifa, Israel “High-Speed Serial Interconnect for NoC “ R. Dobkin, R. Ginosar and A. Kolodny Electrical Engineering Department, Technion, Haifa, Israel “Curing Hotspots in Wormhole NoCs” I. Walter, I. Cidon, R. Ginosar and A. Kolodny Electrical Engineering Department, Technion, Haifa, Israel “Multiple Use-Cases for A Network-on-Chip Design Flow” K. Goossens Philips Research, The Netherlands
14:30-14:45	BREAK
14:45-15:45	Panel: Looking Through the On-Chip Channels Moderator: Steve Furber, University of Manchester, United Kingdom Philippe Martin, Arteris, France Kees Goossens, Philips Research, The Netherlands Christian Sauer, Infineon, Germany Marcello Coppola, ST Microelectronics, France John Bainbridge, Silistix, United Kingdom
15:45-16:30	Planning session for future NoC Symposia General plan for NoC Symposia: Presentation and discussion Ran Ginosar, Technion, Israel Presentation of NoC 2007 Wayne Wolf, Princetin University, United States
16:30	CLOSE

Organizing Committee:

Alex Yakovlev, University of Newcastle-upon-Tyne, UK
Pol Marchal, IMEC, Belgium
Ran Ginosar, Technion, Israel