NoCS 2008
The 2nd IEEE International Symposium on Networks-on-Chip
7th-11th April 2008, Newcastle University, UK. Collocated with Async 2008 and preceded by System Level Interconnect Prediction (SLIP) 2008 on 5th-6th April 2008.
The International Symposium on Networks-on-Chip (NOCS) provides a high quality forum for scientists and engineers to present their latest research findings in the area of NoC-based systems at all levels, from the physical on-chip link level through the network level, and ranging up to systems architecture and application software.
NOCS’08 will be collocated with the 14th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’08) http://async.org.uk/async2008 and the organization and the programs of both symposia will be jointly coordinated, including keynote lectures, tutorials, exhibitions and social events. One of the highlight topics of joint interest will be Low Power.
Conference Schedule and Campus Map
Call For Papers
View in PDF format
Important Dates
- Abstract registration: 12th November 2007
- Full paper submission deadline: 12 midnight CET, 19th November 2007
Note that this deadline is hard and no (automatic) extensions will be granted. - Notification of acceptance: 21st December 2007
- Final version due: 18th January 2008
- Early registration deadline: 7th March 2008
- Late registration deadline: 21st March 2008
Technical Scope
Authors are invited to submit full papers on all aspects of NoCs. Topics of interest include, but are not limited to:
- Network architecture (topology, routing, arbitration,...)
- Power and energy issues in NoC
- NoC case studies, application specific NoC design
- Timing, synchronous /asynchronous communication
- NoC reliability issues
- O/S support for NoC
- Metrics and benchmarks for NoCs
- NoC Network interface issues
- Modeling, simulation, and synthesis of NoCs
- Network-on-chip design methodologies
- NoC Quality of Service
- NoC support for CMP / MPSoC
- NoC support for memory access
- NoCs for FPGAs and structured ASICs
- Programming models
- Mapping of applications onto NoCs
- Novel interconnect links / switches /routers
- Signaling and circuit design for NoC links
- Physical design of interconnect and NoC
- NoC design tools
- Debug & Test of NoC
- Floorplan aware NoC architecture optimisation
Papers should be submitted via the conference web site. The submission should not exceed ten pages in IEEE double column format. Papers that exceed the length limit may not be reviewed. To permit blind review, submissions should not include the author names. Papers will be evaluated by the program committee and reviews will be based on scientific merit, innovation, relevance, and presentation. New-idea papers are encouraged and should be submitted in the specific Seminal Work category. The program committee recognizes that such papers may contain fewer experimental results than papers in established areas. Normal and Seminal Work papers can be accepted either as full papers or as posters. Accepted papers will be included in the conference proceedings published by the IEEE Computer Society.
The authors of the papers accepted for NoCS'08 will be particularly encouraged to submit the extended versions of their papers to the Special Issue of IET Computers and Digital Techniques.
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