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| Projects | |
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SURE Project "SecURE Design Flow" |
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STEP Project "Self-Timed Event Processor" |
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SEDATE Project "SElf-timed DATapath synthEsis" |
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SYRINGE Project "Synchronizer Reliability in the Next Generation of SoC with Multiple Clocks" |
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NEGUS Project "NExt Generation of interconnection technology for mUltiprocessor Soc" |
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SCREEN Project - [Publications] "SeCuRE circuit dEsigN" |
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STELLA Project "Synthesis & TEsting of Low-Latency Asynchronous circuits" |
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COHERENT Project - [Publications] "COmputational HEteRogEneously timed NeTworks" |
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BESST Project "Behavioural Synthesis of Systems with Heterogeneous Timing" |
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MOVIE Project "Model Visualisation for Asynchronous Circuit Design" |
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BREACH Project "Behavioural REfinements for Asynchronous Circuit syntHesis" |
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COMFORT Project - [Publications] "asynchronous COmmunication Mechanisms FOr Real-Time systems" |
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DENT Project "Dependable Embedded system design with petri NeTs" |
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TIMBRE Project "Time-Predicatable Hardware Platforms" |
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ASTI Project "Asynchronous Circuit Synthesis and Testing" |
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HADES Project "Hazard-free Arbiter DESign" |
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"Asynchronous Circuit Design" |
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ASAP Project "Automated Synthesis of Synchronous and Asynchronous Parallel Controllers" |
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"Automated Synthesis of Asynchronous Control Circuits" |
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"Design of Reliable Asynchronous Controllers and Interfaces" |
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Last modified 22/9/2008 by IGC |