Check Hazard is an EDA tool which generates a set of relative timing
constraints for a speed-independent circuit to work correctly when the
isochronic fork timing assumption is relaxed into the intra-operator timing
assumption . Under the intra-operator timing assumption, wires in a fork
that feed into the same gate are considered to be isochronic.
Download and installation
The latest release of the tool can be found on
Check Hazard homepage:
Untar the source files and then run
make from the directory where the sources
are. The binary file
check_hazard will be installed in the subdirectory
Usage of the tool
Check Hazard EDA tool generates a set of relative timing constraints for a
speed-independent circuit to work properly when the isochronic fork timing
assumption is relaxed into the intra-operator timing assumption. It reads a
free-choice STG in ASTG format as the behavior description and a EQN as the
implementation description of a speed-independent circuit.
The tool is run using the following command:
check_hazard [ASTG_file] [EQN_file]
The ASTG file format was specified in the tool petrify .
In the EQN format (currently restricted subset of EQN syntax), each line
contains an equation in the sum of product form to specify the pull-up
function of one gate in the circuit. No brackets are allowed in the
equation. The literals in each product term are connected by the symbol
* and different product terms are connected by the symbol
+. The negation of a signal is suffixed by the symbol
An equation is terminated with the symbol
;. For example, for
a C-element with the input signal A and the negation of signal B,
the equation should be:
C= A*B' + A*C + B'*C;
There is a shell script
run_benchmarks.sh in the directory
benchmarks. It could run a bunch of benchmarks automatically.
Create a subdirectory for each benchmark and put the ASTG (.g) and EQN (.eqn)
in it. The results will be saved in a result.txt file in each subdirectory.
The shell script
clean_benchmarks in the directory
benchmark could remove the result.txt in each subdirectory.
Y. Li, T. Mak, A. Yakovlev:
"Redressing timing issues for speed-independent circuits in deep submicron age",
Proc. Design Automation and Test in Europe (DATE), 2011.
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev:
"Petrify: A tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers",
IEICE Transactions on Information and Systems, 1996.