, where f1,
and f2 are the clock frequencies on either side of the
interface, t and Tw are constants. papers on synchronization and arbitration
"Circuit technology in a large computer system"
D.J. Kinniment, D.G.B. Edwards.
Based on a paper presented at the Joint lERE-IEE-BCS Conference on Computers-Systems
and Technology held in London on 24th to 27th October 1972.. Subsequently published in
The Radio and Electronic Engineer, Vol 43, No 7, July 1973, pages 435 - 441.
SUMMARY In the design of a large high-speed computer, the size of the system
leads to long cable delays for data transmitted between different parts of the machine.
This problem and the interconnexion of a high-speed e.c.l. circuit family are discussed,
and comment is made on future lines of development for technology in high-speed computers.
Priority circuits in a large asynchronous system also present difficulties not usually
encountered in smaller machines and a discussion of how these difficulties arise is
presented.
"Synchronisation and arbitration circuits in digital systems"
D.J. Kinniment, J.V. Woods.
Proc IEE, Vol 123, No 10, October 1976, pages 961 - 966.
Abstract Synchronisation of two independently clocked processor units, or
arbitration between two asynchronous units requesting access to a common resource, can
cause serious time losses in a computer system. The ways in which these problems arise are
considered, and a theoretical basis for calculation of the time losses is presented. The
theory is then correlated with measurements on practical devices, and currently available
methods for minimising the time loss are evaluated. Conditions necessary for prediction of
the performance of synchronisers and arbiters are established and it is shown that design
principles exist which allow the construction of systems with known reliability.
Abstract—Synchronizer circuits are usually characterized by their rate of failure in transmitting data between two independently timed regions. The mean time between failures is assumed to be
, where f1,
and f2 are the clock frequencies on either side of the
interface, t and Tw are constants.
Here t is the time allowed for the synchronizer circuit to reach a stable value after clocking. Previous experimental work has shown that the slope of the histogram relating the logarithm of failure probability to t, is not always constant. We show that these effects, which include an apparent reduction in the value of t in the early part of the histogram to as much as 60% of the final value can be explained by extending the existing theory to take account of initial offsets, and propose a new, more accurate, formula:
where Vs,
Ve, Vt-v, ta and tb
are circuit constants.
Synchronizer
performance depends on achieving a high reliability of synchronization together
with a short time. We show that
commonly used circuits such as the jamb latch, do not produce the best
compromise for very high reliability applications, and that a circuit with a
lower value of t
can be designed.
In
order to confirm that thermal noise does not influence the MTBF against
synchronization time relationship, we have devised an experiment to measure
noise in an integrated CMOS bistable circuit.
We show that the noise exhibits a Gaussian distribution, and is close to
the value expected from thermal agitation.
A.M.
Abas, A. Bystrov, D.J.Kinniment, O.V.Maevsky, G.Russell, and A.V.Yakovlev.
Electronics Letters 7 Nov 2002 Vol. 38 No. 23, pp1437-1438
Abstract—Accurate
measurement of edge time differences down to 10ps or less is required for tests
of timing in digital systems. We
describe a circuit aimed at reliably amplifying these time differences by a
factor between 3 and 10 before measurement to enable greater accuracy.
"Design of an On-Chip Random Number Generator using Metastability"
D.
J. Kinniment, E.G.Chester
Proceedings ESSCIRC2002, Florence, Sept 23-27 2002
Abstract
"Low latency synchronization through speculation"
Enrico Macii, Odysseas G. Koufopavlou, Vassilis Paliouras (Eds.):Abstract.
Synchronization between independently clocked regions in a high performance
system is often subject to latencies of more than one clock cycle. We show how
the latency can be reduced significantly, typically to half the number of clock
cycles required for high reliability, by speculating that a long synchronization
time is not required. The small
number of synchronization metastability times longer than normal are detected,
and subsequent computations re-evaluated, thus maintaining the reliability of
the system.
“Measuring Deep Metastability”
D. Kinniment, K. Heron, and G. Russell, Proc.
ASYNC’06, Grenoble March 2006, pp 2-11.
Abstract Present measurement techniques do not allow synchronizer reliability to be measured in the region of most interest, that is, beyond the first half cycle of the synchronizer clock. We describe methods of extending the measurement range, in which the number of metastable events generated is increased by four orders of magnitude, and events with long metastable times are selected from the large number of more normal events. The relationship found between input times and the resulting output times is dependent on accurate measurement of input time distributions with deviations of less than 10ps. We show how the distribution of D to Clock times at the input can be characterised in the presence of noise, and how predictions of failure rates for long synchronizer times can be made. Anomalies such as the increased failure rates in a master slave synchronizer produced by the back edge of the clock are measured.
J.Zhou, D.J.Kinniment, G. Russell, and A. Yakovlev,,
Proc. ISVLSI’06, pp442-443, March 2006
Abstract