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Chip Gallery

ASIC (1993) | HADIC (2000) | TMC (2003) | SCREEN1 (2005) | SCREEN2 (2006) | SYRINGE1 (2006) | NEGUS1 (2007) | SURE (2008) | SYRINGE2 (2008) | SCRIPT 1 & 2 (2010) | Neural-NOC (2010)

ASIC for Brushless DC drive controller.
Year: 1993
Technology: CMOS gate array 1um with 20,000 gates used.

The architecture is described in:

  • "An Integrated Circuit Controller for Brushless D.C. Drives" D.J. Kinniment, P.P. Acarnley, A.G. Jack. EPE Conference, Florence, 3-6 September 1991
Chip Photo

HADIC Chip contains a range of arbiters (three-way and eight-way ordered arbiters, an eight-way static and dynamic priority arbiters, a comparator with a latch for an A/D converter, Asynchronous Communication Mechanism (3-slot Pool).
Year: 2000
Technology: CMOS 0.6um fabricated via Europractice.
Projects: HADES, COMFORT (funded by EPSRC)

Relevant papers:

  • A. Bystrov, D.J. Kinniment, A. Yakovlev. "Priority Arbiters", Proc. Sixth Int. Symp. on Advanced Research in Asynchronous Circuits and Systems (Async'2000), April 2000, Eilat, Israel, IEEE Computer Society Press, pp. 128-137.
  • F. Xia, A. Yakovlev, D. Shang, A. Bystrov, A. Koelmans, D.J. Kinniment. "Asynchronous Communication Mechanisms Using Self-timed Circuits", Proc. Sixth Int. Symp. on Advanced Research in Asynchronous Circuits and Systems (Async'2000), April 2000, Eilat, Israel, IEEE Computer Society Press, pp. 150-159.
  • D. Shang, F. Xia, A. Yakovlev. "Testing a self-timed asynchronous communication mechanism (ACM) VLSI chip", IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 2001, Gyor, Hungary, 18-20 April 2001. pp. 53-56.
Chip Photo

Chip Layout Chip Photo Chip Photo Chip Photo

TMC Chip contains a time-measurement circuit, including time amplifier and time-to-digital converter.
Year: 2003
Technology: CMOS 0.2 um fabricated by Sun Microsystems
Projects: COHERENT (funded by EPSRC), PhD studentship for M.A.Abas (funded by Malaysian government)

Relevant papers:

  • D.J. Kinniment, O.V. Maevsky, A. Bystrov, G. Russell, A.V. Yakovlev. "On-chip structures for timing measurement and test", Microprocessors and Microsystems, Vol. 27, No. 9, October 2003, pp. 473-483.
  • M.A. Abas, "A New Methodology of an On-Chip Time Measurement Circuit for High-Speed Digital Testing Applications", Ph.D. Thesis, University of Newcastle upon Tyne, Nov. 2003.
Chip layout

SCREEN1 Chip contains AES encryption core design using alternating spacer dual-rail signalling for power balancing (generated from synchronous RTL using in-house tool VeriMap).
Year: 2005
Technology: CMOS AMS 0.35um fabricated by Europractice
Projects: SCREEN (funded by EPSRC)

Relevant papers:

  • J. Murphy and A. Yakovlev. An Alternating Spacer AES Crypto-Processor, Proc. of ESSCIR 2006, Montreux, Switzerland, Sept. 2006, pp. 126-129.
  • D. Sokolov, J. Murphy, A. Bystrov and A.Yakovlev, "Design and Analysis of Dual-Rail Circuits for Security Applications", IEEE Transactions on Computers, Vol. 54, No.4, pp. 449-460, April 2005.
Chip Image

SCREEN2 Chip contains different (synchronous single-rail and power-balanced) versions of AES S-box.
Year: 2006
Technology: CMOS AMS 0.18um fabricated by Europractice
Projects: SCREEN (funded by EPSRC)

Relevant papers:

  • J. Murphy, A. Yakovlev, Power-balanced Asynchronous Logic, Proc. 17th European Conference on Circuit Theory and Design (ECCTD), 29 August - 2 September 2005.
  • J. Murphy, A. Bystrov and A.Yakovlev, Self-Checking Circuits for Security Applications, 11th Annual International Mixed-Signals Testing Workshop (IMSTW’05), Cannes, France, June 2005, pp. 278-285.
Chip image

SYRINGE1 chip contains a robust synchroniser which maintains the value of its metastability time constant in the event of large Vdd variations (with dynamic current control during metastability). The chip also contains an on-chip measurement circuit which extends the measurement of synchronizers into the deep metastability region.
Year: 2006
Technology: CMOS UMC 0.18um fabricated by Europractice
Projects: SYRINGE (funded by EPSRC)

Relevant papers:

  • J. Zhou, D.J. Kinniment, G. Russell and A. Yakovlev, A Robust Synchronizer Circuit, Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'06), Karlsruhe, Germany, March 2006, pp. 442-443.
  • J. Zhou, D.J. Kinniment, G. Russell, and A. Yakovlev, On-Chip Measurement of Deep Metastability in Synchronizers, IEEE Journal of Solid-State Circuits, Vol. 43, No. 2, 2008.
Chip layout Chip Photos with electron microscope Chip ebeam image

NEGUS1 Phase-Encoding Demonstrator Chip. Contains different "flavours" of phase-encoding signalling to evaluate feasibility and performance of the scheme.
Year: 2007
Technology: UMC 0.13um through Europractice
Projects: NEGUS (EPSRC Grant EP/C512812/1)

Relevant papers:

  • D'Alessandro, C. (2007), Fast point-to-point serial link using Phase-Encoding, in 'Proceedings of the 3rd UK Embedded Forum'.
  • D'Alessandro, C.; Bystrov, A. & Yakovlev, A. (2007), 'Improved phase-encoding signalling', Electronics Letters 43(4), 216--217.
  • D'Alessandro, C.; Mokhov, A.; Bystrov, A. & Yakovlev, A. (2007), Delay/Phase Regeneration Circuits, in 'Proceedings. 13th International Symposium on Asynchronous Circuits and Systems. ASYNC 2007'.
  • D'Alessandro, C.; Shang, D.; Bystrov, A. & Yakovlev, A. (2005), PSK Signalling on SoC Buses, in 'Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Proceedings of PATMOS 2005', Springer .
  • D'Alessandro, C.; Shang, D.; Bystrov, A.; Yakovlev, A. & Maevsky, O. (2006), Multiple-Rail Phase-Encoding for NoC, in 'Asynchronous Circuits and Systems, 2006. 12th IEEE International Symposium on', pp. 107--116.
Chip layout Package layout Chip ebeam image of pads

SURE Galois Encoded Logic AES-128 IP core Proof of Concept Chip. Implements side-channel secure "high radix" AES-128 encryption in a fully parallel architecture to investigate the security and study the market feasibility of the technology.
Year: 2008
Technology: UMC 0.13um through Europractice
Projects: SURE (EPSRC Grant EP/F016786/1)

Chip photo Chip photo

SYRINGE2 Time-to-Digital Converter and Neuron Chip.
A High Resolution Flash Time-to-Digital Converter (TDC) was developed on a 130nm chip to investigate timing faults caused by the violation of internal timing parameters, such as clock jitter, clock skew and set-up and hold times. The TDC offers the possibility of measuring these timing parameters on-chip to the order of a single picosecond. The chip also contains demonstration circuits of a Leaky Integrate-and-Fire Neuron and an Asynchronous Pulse Generator for use in a biologically inspired reconfigurable neural network.

Investigation into the cause of timing problems cannot satisfactorily be undertaken by external equipment, due to the remoteness of external equipment from the source of the problem. Therefore, on-chip measurement circuits such as Time-to-Digital Converters (TDCs) are ideal for measuring accurately the relationship between two or more physical events to establish whether they operate according to specifications. In addition the method has the effect of reducing the measurement errors introduced by process, temperature and voltage variation, by implementing a statistical technique which relies on counting the number of high outputs.

Year: 2008
Technology: UMC 0.13um through Europractice
Project: SYRINGE (EPSRC Grant EP/C007298/1)
Contacts: Nikolaos Minas - Nikolaos.Minas@ncl.ac.uk, Robin Emery - r.a.emery@ncl.ac.uk

Chip photo Chip photo Chip photo Chip photo Chip photo

Script 1 & 2
The chip designs implemented two co-processors with a AMBA-APB interface, a AES-128 encrypter (SCRIPT1) and 64-bit Floating Point Unit (SCRIPT2), and proved to be working correctly. They implemented the research conducted and by products of SCRIPT, EPSRC's Follow-on-Fund commercialization fund, where we came first against 113 other red-brick universities in 2008 in collaboration with Renesas Labs, Japan and raising 135k.
The chips were a proof-of-concept silicon to support two new patent disclosures to Newcastle's Business Development Directorate Unit.

Year: 2010
TSMC 90nm through Europractice mini@sic service
Projects: SURE and SCRIPT (funded by EPSRC)
Contact: Julian Murphy, j.p.murphy@ncl.ac.uk

Chip photo Chip photo

Neural-NOC
A demonstration chip in 90nm CMOS containing a reconfigurable neural network structure with hybrid interconnect. Consisting of 15 configurable blocks for neural network simulation connected by a configurable interconnect, the chip measures 1.8x1.8mm, contains over 180 thousand cells and took the best part of 4 months of work to implement. Each block contains one neuron model and ten synapses with learning capability. To complement the local routing resource, a single Network-on-Chip tile is superimposed; packets can be routed on and off chip for testing and demonstration. The chip is intended as a demonstration of a concept for a hardware neural network simulation platform for biological neural network models - which are massively parallel but have mostly local connectivity - for which a hybrid communication structure should provide adequate local resources that can scale as the network simulation grows larger.

Year: 2010
Technology: TSMC 90nm through Europractice mini@sic service
Project:
Contact: Robin Emery, r.a.emery@ncl.ac.uk

Relevant papers:
R. Emery, A. Yakovlev and G. Chester, Connection-Centric Network for Spiking Neural Networks, Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCs 2009), San Diego, CA, USA, May 2009, IEEE, pp. 144-152.

Chip photo Chip photo Chip photo


Last modified 12/07/2010 by IGC