PER Ashur Rafiev
Abstract: PER supports the exploration of parallelization scaling and DVFS scaling when trading off system performance, energy consumption, and reliability.
[ http://async.org.uk/prime/PER/ ].

Check Hazard Yu Li
Check Hazard generates a set of relative timing constraints for a speedindependent circuits which allow them to operate correctly when the isochronic fork timing assumption is relaxed into the intraoperator timing assumption.
[ http://async.org.uk/tools/checkhazard/ ].

Workcraft Ivan Poliakov, Arseniy Alekseyev, Stanislavs Golubcovs, Andrey Mokhov, Danil Sokolov
A large number of models that are employed in the field of concurrent systems design, such as Petri nets, Signal Transition Graphs (STGs), Conditional Partial Order Graphs (CPOGs), Structured Occurrence Nets (SONs), dataflow structures, gatelevel circuits, etc.  all have an underlying static graph structure. Their semantics, however, is defined using additional entities, e.g. tokens or node/arc states, which in turn form the overall state of the system. We jointly refer to such formalisms as Interpreted Graph Models. The similarities in notation allow for links between different models to be created, such as interfaces between different formalisms or conversion from one model type into another, which greatly extend the range of applicable analysis techniques.
Workcraft is designed to provide a flexible common framework for development of Interpreted Graph Models, including visual editing, (co)simulation and analysis. The latter can be carried out either directly or by mapping a model into a behaviourally equivalent model of a different type (usually a Petri Net). Hence the user can design a system using the most appropriate formalism (or even different formalisms for the subsystems), while still utilising the power of Petri Net analysis techniques. The tool is platformindependent, highly customisable by means of plugins, and is freely available for academic use.
[ http://workcraft.org/ ].

RMMixed Ashur Rafiev
RMMixed is a mixed radix synthesis tool based on fixed polarity ReedMuller expansions over Galois field arithmetic [1]. Taking into account the actual values for switching energy and area for arithmetic components the synthesis tool searches for the optimal solution with respect to the gate level characteristics.
[ http://async.org.uk/sure/rmmixed/ ].

VERISYN Frank Burns
Asynchronous High Level Synthesis Tool.
[ http://async.org.uk/besst/verisyn/ ].

Verimap Danil Sokolov
VeriMap is a design kit for converting a singlerail RTL netlists into a dualrail circuits resistant to DPA attacks.
[ http://async.org.uk/screen/verimap/ ].

PN2DCs Delong Shang
Petri nets to David Cell Hardware Circuit.
[ http://async.org.uk/besst/pn2dcs/ ].

OptiMist Danil Sokolov
OptiMist (Optimise and Map) is a package of tools that optimise Signal Transition Graph specifications and map them into asynchronous circuits.
[ http://async.org.uk/besst/optimist/ ].

ConfRes Agnes Madalinski
Interactive Coding Conflict Resolver based on Core Visualisation The tool supports manual resolution of coding conflicts in asynchronous circuit specification given as Signal Transition Graphs (STGs) and displays them as partial orders (finite and complete prefixes of STG unfoldings). The manual approach although efficient requires a significant effort from the designer. The tool ConfRes assists the designer by visualising the conflict cores, their superposition and the constraints on signal insertion.
[ http://async.org.uk/besst/confres/ ].

Indie Danil Sokolov
Indie is a software tool which computes the smallest fully indicating implementation of a circuit.
[ http://async.org.uk/screen/indie/ ].

LESTA Agnes Madalinski
LESTA stands for LogicalEffortbased Static Timing Analysis  "lesta" also is the female adjective for "quick" in Italian.
LESTA is a tool which, given an STG and its relative Verilog netlist, outputs the delay information
for each inputtooutput path of the STG . These delays are calculated using the Logical Effort method.
Alternatively the tool can calculate dthe delay information using characterised delay information. The tool requires a library file
which contains the Logical Effort and characterised information for all the gates present in the Verilog netlist.
[ http://async.org.uk/stella/lesta/ ].

ProtoDe Danil Sokolov
ProtoDe is a software tool for protocol decomposition of Signal Transition Graphs (STGs).
[ http://async.org.uk/stella/protode/ ].

TeLLA Deepali Koppad
TeLLA stands for TEsting of Low Latency Asynchronous circuits.
TeLLA is a tool for testing circuits obtained by direct mapping. TeLLA reads in a verilog netlist and generates a set of test vectors required to test the circuit. The verilog netlist must be obtained using the OptiMist tool available at [http://async.org.uk/besst/optimist/ ]. Using the t (testing) option in OptiMist a netlist including the test features can be obtained.
TeLLa provides a table consisting of a list of test vectors, it also consists information on the time required to apply one test vector to the circuit, total number of test vectors and the total time to apply all the test vectors.
[ http://async.org.uk/stella/tella/ ].
