Registration: Go to DATE 2006 registration site and select either the entire conference or Friday Workshop W2.

Accommodation: Go to DATE 2006 accommodation site.

Advances in semiconductor technology, design re-use and tools are enabling designers to put complex, massively parallel multiprocessor systems on a single chip. The idea of packet-switching Networks on a Chip (NoC) offers more flexibility, robustness and better resource utilisation than what is provided by traditional bus-based architectures. NoCs are poised to be an alternative to buses, but should they rather be seen complementary than alternative in the longer term? What kind of new communication paradigms and signaling schemes are more suited for NoCs in order to battle inherent signal integrity and soft errors? Are there fundamental issues about on-chip interconnects that will limit performance and dependability of communication as Moore's Law gradually runs out of steam within the next decade? What about new technologies such as optical interconnects?

These and other questions will be in the centre of this workshop, which will bring together researchers actively working on future interconnects and NoCs. The workshop is also keen to invite hardware and system engineers interested in new developments in this area. In a final panel, experts in the field will address the challenges and opportunities for on-chip interconnect paradigms and project their vision on the current developments in academic and industrial research.

The workshop will serve to launch a new series of high quality symposia, targetted at Networks on Chip and Interconnects. The need for such a dedicated forum is increasingly recognised due to the steady growth in research activity and contributions that are currently spread over multiple conferences in diverse areas such as architecture, circuits, CAD and networking. It will also provide an excellent thematic framework for interaction between industry and academia.


Workshop Goal
To discuss problems and opportunities, present points of view and develop collective vision for the future of on-chip interconnects and communications
To survey research by the leading research groups working in this area around the world
To plan a new international symposium on NoCs and interconnects

Workshop Program


Welcome and Introduction


Keynote: NoCs: Vision, reality, trends
Luca Benini, DEIS - Bologna U, Italy


Session 1: Advances in NoCs (invited presentations)
Chair: Ran Ginosar, Technion, Israel

·         Networks and Applications: Are Application-Specific Networks Worth the Trouble?
Wayne Wolf, Princeton U, United States




Session 2: Advances in On-Chip Interconnects (invited presentations)
Chair: Pol Marchal, IMEC, Belgium

·         Potential impact of emerging System-in-Packaging technologies on system design
Eric Beyne, IMEC, Belgium


Introducing Research Groups
Chair: Avinoam Kolodny, Technion, Israel


  • John Bainbridge, Silistix, United Kingdom
  • Israel Cidon, Technion, Israe
  • Marcello Coppola, ST Microelectronics, France
  • Shinobu Fujita, Toshiba, Japan
  • Kees Goossens, Philips Research, The Netherlands
  • Graham Hellestrand, VaST Systems, United States
  • Andre Ivanov, UBC, Canada
  • Shashi Kumar, Jönköping U, Sweden
  • Philippe Martin, Arteris, France
  • Radu Marculescu, CMU, United States
  • Jari Nurmi, Tampere U. Tech., Finland
  • Ian O’Connor, LEOM, France
  • Christer Svensson, Linköping U, Sweden
  • Hoi-Jun Yoo, KAIST, Korea




Poster Session

Poster Abstracts

This session will enable direct interactions among all researchers. Its goals are to get to know each other and each other's work, and to create opportunities for research collaborations.

  1. “EEG Biomedical Sensors Network on Chip (EBSNOC)”

M. Saleh and Axel Jantsch

Royal Institute of Technology (KTH), Sweden

  1. “Evaluation of On-chip Networks Using Deflection Routing”

Z. Lu, M. Zhong and A. Jantsch

Royal Institute of Technology, Sweden

  1. “Utilizing NoC Switches as BIST-structures in 2D Mesh Network-on-Chip”

K. Petersén1, J. Öberg1, S. Evain2 and J. Diguet2

1 Royal Institute of Technology (KTH), Sweden

2 University of South Brittany, France

  1. “Emerging Networks on Chip: Lessons Learned to Win the Future”

I. Al Khatib

Royal Institute of Technology, , Sweden

  1. “Interoperability Protocol and Algorithms for Network-on-Chip Autonomous-System Communications for the Next Generation Biomedical Sensor-Networks”

I. Al Khatib1, A. Jantsch1, R. Nabiev2 and L. O. Alima3

1 Royal Institute of Technology, Sweden

2 Karolinska University Hospital Huddinge, Sweden

3 Université de Mons-Hainaut, Belgium

  1. “Synchronous Latency Insensitive Design in Ęthereal NoC

X. Ru1, J. Dielissen2, C. Svensson3 and K. Goossens2

1 Philips Semiconductors, Switzerland

2 Philips Research, The Netherlands

3 Linköping University, Sweden

  1. “An improved method for delay fault testing of NoC interconnections”

T. Bengtsson1, S. Kumar1, A. Jutman2 and R. Ubar2

1 Jönköping University, Sweden

2 Tallinn University of Technology, Estonia

  1. “STAR : An Efficient Routing Strategy for NoC with Mixed QoS Requirements”

D. Andreasson and S. Kumar

Jönköping University, Sweden

  1. “On Options for Accessing Regions in NoC

R. Holsmark and S. Kumar

Jönköping University, Sweden

  1. “Application Parallelism Exploitation using NoC with Multithreaded Processors”

R. Pop and S. Kumar

Jönköping University, Sweden

  1. “Versatile XGFT Network-On-Chip with Improved Fault-Tolerance for Multi-Processor Systems-on-Chip”

H, Kariniemi and J. Nurmi

Tampere University of Technology, Finland

  1. “Fault-Diagnosis-And-Repair System for Improving the Fault-Tolerance and Manufacturability of MPSoCs

H. Kariniemi and J. Nurmi

Tampere University of Technology, Finland

  1. “Exploration of CDMA-Based Network-on-Chip”

X. Wang and J. Nurmi

Tampere University of Technology, Finland

  1. NoC-Based Platform Implementation on FPGA”

T. Ahonen, J. Kylliäinen, C. Brunelli and Jari Nurmi

Tampere University of Technology, Finland

  1. “A Hierarchical Approach to Network-on-Chip”

T. Ahonen and J. Nurmi

Tampere University of Technology, Finland

  1. “PROTEO – A Flexible Network-on-Chip Scheme”

T. Ahonen, D. Sigüenza-Tortosa * and J. Nurmi

Tampere University of Technology, Finland

* Complutense University of Madrid, Spain

  1. SystemC Simulation Model of a Flexible Network-on-Chip”

S. Määttä and J. Nurmi

Tampere University of Technology, Finland

  1. “Network-on-Chip Generation and Optimization Tool”

T. Ahonen, H. Bin and J. Nurmi

Tampere University of Technology, Finland

  1. “FAUST, an Asynchronous Network-on-Chip based Architecture for Telecom Applications”

P. Vivet, F. Clermidy, D. Lattard


  1. “Heterogeneous integration of light sources on an SOI waveguide platform for photonic interconnects on CMOS (PICMOS)”

G. Roelkens1, J. Van Campenhout1, D. Van Thourhout1, R. Baets1, P. Rojo-Romeo2, C. Seassal2, P. Regreny2, P. Viktorovitch2, I. O’Connor2, L. Di Cioccio3 and J. Fedeli3

1 Ghent University Belgium

2 Ecole Centrale de Lyon France


  1. “Optical interconnect for on-chip data communication”

I. O’Connor1, F. Tissafi-Drissi1, D. Navarro1, F. Mieyeville1, F. Gaffiot1, J. Dambre2, M. De Wilde2, D. Stroobandt2 and D. Van Thourhout3

1 Ecole Centrale de Lyon, France

2 Ghent University, Belgium

3 IMEC / Ghent University, Belgium

  1. “Methodology, benefits and tools for NoC topology exploration”

P. Martin  and J. Lecler

Arteris SA, France

  1. “µSpider NoC Road Map”

S. Evain and  J. Diguet,

University of South Brittany, France

  1. “Modeling and synthesis of Asynchronous Network on Chip using SystemC

C. Koch-Hofer and M. Renaudin

TIMA, France

  1. STNoC™: An Evolution Towards MPSoC Era”

M. Coppola¹, C. Pistritto², R. Locatelli¹ and Alberto Scndurra²

¹ STM, AST Grenoble Lab, France

² STM, HPC, Italy

  1. “Design of a simple clockless Network-on-Chip for an audio DSP chip”

M. Stensgaard1, T. Bjerregaard1, J. Sparsų1 and J. Pedersen2

1 Technical University of Denmark (DTU)

2 William Demant Holding

  1. Clockless On-Chip Networks and MANGO”

T. Bjerregaard, J. Sparsų and M. Stensgaard

Technical University of Denmark, Denmark

  1. “Multiple-rail phase-encoding for NoC

C. D'Alessandro1, D. Shang1, A. Bystrov1, A. Yakovlev1, O. Maevsky 2

1 University of Newcastle upon Tyne, UK

2 Intel Labs, Moscow

  1. “Design of fast and reliable synchronisers for NoCs “

J. Zhou, D. Kinniment, G. Russell, and A. Yakovlev

University of Newcastle upon Tyne, UK

  1. CHAINworks™ – an EDA tool suite and IP libraries for self-timed interconnect design synthesis”

J. Bainbridge, A. Bardsley and R. McGuffin,

Silistix, United Kingdom

  1. “Towards a Communication-Centric Design Methodology”

A. Banerjee, R. Francis, J. Lee, J. May, S. W. Moore and R. D. Mullins

Computer Laboratory, University of Cambridge, United Kingdom

  1. “BIST for NoC Interconnects”

C. Grecu11, P. Pande2, A. Ivanov1 and R. Saleh1

1 University of British Columbia, Canada;

2 Washington State University, United States

  1. “A Distributed, Interleaved FIFO for SoC Interconnect”

S. Sood, M. Greenstreet and R. Saleh

University of British Columbia

  1. “Clock Synchronization in NoCs using Distributed FIFOs

P. Pande and J. Nyathi

Washington State University, United States

  1. “A 20Gb/s Transceiver for Network-On-Chip”

Z. Asgar, J. Zou, P. Jain, R. Kamath and R. Harjani

University of Minnesota, United States

  1. “Constraint-Driven Communication Synthesis of Networks On-Chip”

A. Pinto, L.P. Carloni and A.L. Sangiovanni-Vincentelli

U.C. Berkeley, United States

Columbia University, United States

  1. “Application-Specific Networks-on-Chips”

J. Xu and W. Wolf

Princeton University, United States

  1. “Introduction to the Princeton Polaris Project”

V. Soteriou, N. Eisley, H. Wang, B. Li and L. Peh

Princeton University, United States

  1. NoC Performance Optimization via Long-range Link Insertion”

U. Ogras and R. Marculescu

Carnegie Mellon University, United States

  1. “Performance Enhancement through Early Release and Buffer Optimization in Network-on-Chip Router Architectures”

J. Kim D. Park C. Nicopoulos N. Vijaykrishnan and C. Das

The Pennsylvania State University, United States

  1. “Empirical Optimization of Multiprocessor Systems and their Heterogeneous Communication Fabrics

G. Hellestrand, J. Torossian and C. Alford

VaST Systems, United States

  1. “Spatial Division Multiplexing: A Novel Approach for Guaranteed Throughput on NoCs”

A. Leroy1/2, P.Marchal1, F. Robert 2 and F. Catthoor1/3

1 IMEC Belgium

2 VUB Belgium

3 KUL Belgium

  1. “A Flexible System Level Design Methodology Applied to NoC

A. Vander Biest, A. Leroy and F. Robert

ULB Belgium

  1.  “Extended Global Interconnect Architecture for Nano-CMOS Technologies”

J.Balachandran1, S.Brebels1, G.Carchon1, M.Kuijk2, W.De Raedt1, B.Nauwelaers 3 and E.Beyne1,

1 IMEC Belgium

2 VUB Belgium

3 KUL Belgium

  1. “Dynamic Time-Slot Allocation for Networks on Chip with TDMA QoS

T. Marescaux1, B. Brick“e1,2, P. Debacker1,2, V. Nollet1, H. Corporaal3

1IMEC V.Z.W., Belgium

2Katholieke Universiteit Leuven, Belgium

3Technical University Eindhoven ( TU/e ), The Netherlands

  1. “Reconfigurable Optical Networks for On-Chip Multiprocessors”

W. Heirmana, J. Dambrea, I. O’Connorb, J. Van Campenhouta

aELIS, Ghent University, Belgium;

bLEOM, Ecole Centrale de Lyon, France

  1. “Introduction to KAIST BONE project”

K. Lee, S. Lee, D. Kim, K. Kim, J. Kim and H. Yoo

Korea Adv. Inst. of Science and Technology (KAIST), Korea

  1. “Novel Performance of Three-dimensional (3D) On-chip Crossbar Bus using non-Silicon Transistors”

S. Fujita1/2, K. Abe1, K. Nomura1 and T. Lee3,

1 Frontier Research Laboratory, Toshiba, Kawasaki, Japan

2 Toshiba America Research, United States

3 Stanford University, United States

  1. “Dynamic Multi-grain Pipelined Interconnect”

M. Imai, T. Azuma, K. Watanabe and T. Nanya

Res. Ctr for Adv. Sci. and Tech., The U. of Tokyo, Japan

  1. QoS Oriented Configurable Network on Chip”

M. Al Faruque, X. Ye, G. Weiss and J. Henkel

University of Karlsruhe, Germany

  1. “A Lightweight NoC for the NOVA Packet Processing Platform”

C. Sauer1, M. Gries1, S. Dirk1, J.-C. Niemann2, M. Porrmann2, U. Rückert2

1 Infineon Technologies, Germany

2 HNI Paderborn, Germany

  1. “A dedicated communication layer for Power Management of NoC based SoCs

N. Genko1, D. Atienza1/2, A. Aquaviva1 and G. De Micheli1

1 EPFL, Switzerland

2 DACYA/UCM, Spain.

  1. “HW/SW Partitioning and Interface Synthesis in NoCs”

F. Regazzoni and M. Lajolo

ALaRI - USI, Lugano, Switzerland

NEC Laboratories America, Princeton, United States

  1. “Recovering from Transient Memory Failures in NoC Designs by Software Data Restore”

F. Angiolini, D. Atienzaz, S. Murali, L. Benini, G. De Micheli

DEIS, University of Bologna, 40136 Bologna, Italy

  1. “Buffer output capacitance effect on NoC line drivers performance”

G. Cappuccino, A. Pugliese, G. Cocorullo

DEIS-University of Calabria, Italy

  1. QNoC: QoS Network on Chip”

E. Bolotin, I.Cidon, R. Ginosar and  A.Kolodny

Electrical Engineering Department, Technion, Haifa, Israel

  1. “Efficient Link Capacity and QoS Design for Network-on-Chip”

Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny

Electrical Engineering Department, Technion, Haifa, Israel

  1. “High-Speed Serial Interconnect for NoC   “

R. Dobkin, R. Ginosar and A. Kolodny

Electrical Engineering Department, Technion, Haifa, Israel

  1. “Curing Hotspots in Wormhole NoCs”

I. Walter, I. Cidon, R. Ginosar and A. Kolodny

Electrical Engineering Department, Technion, Haifa, Israel

  1. Multiple Use-Cases for A Network-on-Chip Design Flow”

K. Goossens

Philips Research, The Netherlands




Panel: Looking Through the On-Chip Channels
Moderator: Steve Furber, University of Manchester, United Kingdom

  • Philippe Martin, Arteris, France
  • Kees Goossens, Philips Research, The Netherlands
  • Christian Sauer, Infineon, Germany
  • Marcello Coppola, ST Microelectronics, France
  • John Bainbridge, Silistix, United Kingdom


Planning session for future NoC Symposia




Organizing Committee: